
CONTENTS
Slave Controller – Technology I-VII
5.8.2 Far-End-Fault (FEF) 24
5.8.3 ESCs with native FX support 25
5.8.4 ESCs without native FX support 25
5.9 Gigabit Ethernet PHYs 25
5.10 MII Management Interface (MI) 26
5.10.1 PHY Addressing/PHY Address Offset 26
5.10.2 Logical Interface 28
5.10.3 MI Protocol 29
5.10.4 Timing specifications 29
5.11 MII management example schematic 30
5.12 Ethernet Termination and Grounding Recommendation 31
5.13 Ethernet Connector (RJ45 / M12) 32
5.14 Back-to-Back MII Connection 33
5.14.1 ESC to ESC Connection 33
5.14.2 ESC to Standard Ethernet MAC 34
6 EBUS/LVDS Physical Layer 35
6.1 Interface 35
6.2 EBUS Protocol 36
6.3 Timing Characteristics 36
6.4 Standard EBUS Link Detection 37
6.5 Enhanced EBUS Link Detection 37
6.6 EBUS RX Errors 38
6.7 EBUS Low Jitter 38
6.8 EBUS Connection 38
7 FMMU 39
8 SyncManager 41
8.1 Buffered Mode 42
8.2 Mailbox Mode 43
8.2.1 Mailbox Communication Protocols 43
8.3 PDI register function acknowledge by Write 44
8.4 Interrupt and Watchdog Trigger Generation, Latch Event Generation 44
8.5 Single Byte Buffer Length / Watchdog Trigger for Digital Output PDI 45
8.6 Repeating Mailbox Communication 45
8.7 SyncManager Deactivation by the PDI 46
9 Distributed Clocks 47
9.1 Clock Synchronization 47
9.1.1 Clock Synchronization Process 49
9.1.2 Propagation Delay Measurement 50
9.1.3 Offset Compensation 55
9.1.4 Resetting the Time Control Loop 56
9.1.5 Drift Compensation 56
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