Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Instrukcja Użytkownika

Version 1.0 Date: 2015-01-20 Hardware Data Sheet Section III ET1815 / ET1816 Slave Controller IP Core for Xilinx® FPGAs Release 3.00k Sectio

FIGURES III-X Slave Controller – IP Core for Xilinx FPGAs FIGURES Figure 1: EtherCAT IP Core Block Diagram ...

Ethernet Interface III-88 Slave Controller – IP Core for Xilinx FPGAs EtherCAT devicenRGMII_LINKCLK25_2NSRGMII_RX_CLKRGMII_RX_CTL_DATA_DDR_NRESETRGMI

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-89 9.4.2 RGMII example schematic Refer to chapter 8.5.3 for more information on

Ethernet Interface III-90 Slave Controller – IP Core for Xilinx FPGAs 9.4.4.1 TX_CLK Delay in PHY Some PHYs offer RGMII-ID, which means, the TX_CLK

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-91 10 PDI Description Table 43: Available PDIs for EtherCAT IP Core PDI number 0x0

PDI Description III-92 Slave Controller – IP Core for Xilinx FPGAs 10.1 Digital I/O Interface 10.1.1 Interface The Digital I/O PDI is selected with

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-93 10.1.2 Configuration The Digital I/O interface is selected with PDI type 0x04 i

PDI Description III-94 Slave Controller – IP Core for Xilinx FPGAs 32Output registerDigital I/O output data register 0x0F00:0x0F03Watchdog&3232EO

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-95 10.1.7 SOF SOF indicates the start of an Ethernet/EtherCAT frame. It is asserte

PDI Description III-96 Slave Controller – IP Core for Xilinx FPGAs SOFDATAInput DATAtSOF_to_DATA_setuptSOFtSOF_to_DATA_hold Figure 39: Digital Input:

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-97 OUTVALIDDATAtDATA_to _OUTVALIDOutput DATAtOUTVALIDtOE_EXT_to _DATA_inv alidOE_EX

FIGURES Slave Controller – IP Core for Xilinx FPGAs III-XI Figure 61: AXI Read Access ...

PDI Description III-98 Slave Controller – IP Core for Xilinx FPGAs 10.2 SPI Slave Interface 10.2.1 Interface An EtherCAT device with PDI type 0x05

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-99 10.2.3 SPI access Each SPI access is separated into an address phase and a data

PDI Description III-100 Slave Controller – IP Core for Xilinx FPGAs 10.2.5 Commands The command CMD0 in the second address/command byte may be READ,

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-101 10.2.8.1 Read Wait State Between the last address phase byte and the first dat

PDI Description III-102 Slave Controller – IP Core for Xilinx FPGAs 10.2.10 2 Byte and 4 Byte SPI Masters Some SPI masters do not allow an arbitrary

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-103 10.2.11 Timing specifications Table 52: SPI timing characteristics IP Core Para

PDI Description III-104 Slave Controller – IP Core for Xilinx FPGAs Table 53: Read/Write timing diagram symbols Symbol Comment A15..A0 Address bits [

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-105 C00SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late

PDI Description III-106 Slave Controller – IP Core for Xilinx FPGAs C00SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late s

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-107 SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sa

ABBREVIATIONS III-XII Slave Controller – IP Core for Xilinx FPGAs ABBREVIATIONS µC Microcontroller ADR Address AL Application Layer AMBA® Advanced M

PDI Description III-108 Slave Controller – IP Core for Xilinx FPGAs SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late samp

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-109 10.3 Asynchronous 8/16 bit µController Interface 10.3.1 Interface The asynchr

PDI Description III-110 Slave Controller – IP Core for Xilinx FPGAs 10.3.3 µController access The 8 bit µController interface reads or writes 8 bit

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-111 10.3.6 µController access errors These reasons for µController access errors a

PDI Description III-112 Slave Controller – IP Core for Xilinx FPGAs 10.3.8 Connection with 8 bit µControllers If the ESC is connected to 8 bit µCont

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-113 10.3.9 Timing Specification Table 57: µController timing characteristics IP Co

PDI Description III-114 Slave Controller – IP Core for Xilinx FPGAs Parameter Min Max Comment tBUSY_to_WR_CS 0 ns11 WR or CS deassertion after BUSY

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-115 BHE1CSBHEWRRDDATABUSYADR1ADRtWR_activetCS_delaytWR_delaytADR_BHE_DATA_holdDATA

PDI Description III-116 Slave Controller – IP Core for Xilinx FPGAs BHE1CSBHEWRRDDATABUSYADR1ADRtWR_activetCS_delaytWR_delaytADR_BHE_DATA_holdDATA1tA

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-117 10.4 PLB Slave Interface 10.4.1 Interface The PLB v4.6 slave PDI is selected

Overview Slave Controller – IP Core for Xilinx FPGAs III-1 1 Overview The EtherCAT IP Core is a configurable EtherCAT Slave Controller (ESC). It t

PDI Description III-118 Slave Controller – IP Core for Xilinx FPGAs Signal Direction Description Signal polarity PLB_IRQ_MAIN OUT Interrupt act. high

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-119 10.4.3 Timing specifications Table 60: PLB timing characteristics Parameter Mi

PDI Description III-120 Slave Controller – IP Core for Xilinx FPGAs PLB_SPLB_CLKPLB_ABusADRPLB_RNWPLB_Sl_RdDackPLB_Sl_RdCompPLB_Sl_rdDBusDATAtReadPLB

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-121 10.5 AXI4/AXI4 LITE On-Chip Bus 10.5.1 Interface The AXI4 Slave PDI is selec

PDI Description III-122 Slave Controller – IP Core for Xilinx FPGAs Signal Direction Description Channel Signal polarity PDI_AXI_ARPROT[2:0] INPUT Re

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-123 10.5.2 Configuration The AXI4 interface has PDI type 0x80 in the PDI control r

PDI Description III-124 Slave Controller – IP Core for Xilinx FPGAs 10.5.4 Timing specifications The AXI PDI accepts read and write accesses simulta

PDI Description Slave Controller – IP Core for Xilinx FPGAs III-125 CLK_PDI_EXTARREADYADRARADRRVALIDRDATADATAtReadARVALIDtClk Figure 61: AXI Read A

Distributed Clocks SYNC/LATCH Signals III-126 Slave Controller – IP Core for Xilinx FPGAs 11 Distributed Clocks SYNC/LATCH Signals For details about

SII EEPROM Interface (I²C) Slave Controller – IP Core for Xilinx FPGAs III-127 12 SII EEPROM Interface (I²C) For details about the ESC SII EEPROM

Overview III-2 Slave Controller – IP Core for Xilinx FPGAs 1.1 Frame processing order The frame processing order of the EtherCAT IP Core is as follo

Electrical Specifications III-128 Slave Controller – IP Core for Xilinx FPGAs 13 Electrical Specifications Table 68: AC Characteristics Symbol Param

Synthesis Constraints Slave Controller – IP Core for Xilinx FPGAs III-129 14 Synthesis Constraints The following table contains basic IP Core cons

Synthesis Constraints III-130 Slave Controller – IP Core for Xilinx FPGAs Example User Constraints File (UCF) ######################## ### Global CLK

Synthesis Constraints Slave Controller – IP Core for Xilinx FPGAs III-131 ################## ### MII Port 2 ### ################## ### Receive clo

Appendix III-132 Slave Controller – IP Core for Xilinx FPGAs 15 Appendix 15.1 Support and Service Beckhoff and our partners around the world offer

Overview Slave Controller – IP Core for Xilinx FPGAs III-3 1.2 Scope of this document Purpose of this document is to describe the installation and

Overview III-4 Slave Controller – IP Core for Xilinx FPGAs 1.4 Target FPGAs The EtherCAT IP Core for Xilinx® FPGAs is targeted at these FPGA familie

Overview Slave Controller – IP Core for Xilinx FPGAs III-5 1.6 Tested FPGA/Designflow combinations The EtherCAT IP Core has been synthesized succe

Overview III-6 Slave Controller – IP Core for Xilinx FPGAs 1.7 Release Notes EtherCAT IP Core updates deliver feature enhancements and removed restr

Overview Slave Controller – IP Core for Xilinx FPGAs III-7 Version Release notes 3.00f (2/2014) Restrictions of previous versions which are removed

DOCUMENT ORGANIZATION III-II Slave Controller – IP Core for Xilinx FPGAs DOCUMENT ORGANIZATION The Beckhoff EtherCAT Slave Controller (ESC) docum

Overview III-8 Slave Controller – IP Core for Xilinx FPGAs Version Release notes 3.00j (9/2014) Enhancements:  An example design for the Xilinx Zyn

Overview Slave Controller – IP Core for Xilinx FPGAs III-9 1.7.1 Major differences between V2.04x and V3.00x The EtherCAT IP Core V3.00x versions

Overview III-10 Slave Controller – IP Core for Xilinx FPGAs 1.8 Design flow The design flow for creating an EtherCAT Slave Controller based on the E

Overview Slave Controller – IP Core for Xilinx FPGAs III-11 1.9 IP Core Evaluation The EtherCAT IP Core for Xilinx FPGAs supports IP core evaluati

Overview III-12 Slave Controller – IP Core for Xilinx FPGAs 1.10 Simulation A behavioral simulation model of the EtherCAT IP core is not available b

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-13 2 Features and Registers 2.1 Features Table 7: IP Core Feature Details

Features and Registers III-14 Slave Controller – IP Core for Xilinx FPGAs Feature IP Core Xilinx® V3.00k IP Core Xilinx® V3.00c-3.00j Wait State by

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-15 Feature IP Core Xilinx® V3.00k IP Core Xilinx® V3.00c-3.00j Propagation

Features and Registers III-16 Slave Controller – IP Core for Xilinx FPGAs 2.2 Registers An EtherCAT Slave Controller (ESC) has an address space of 6

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-17 Address Length (Byte) Description IP Core V3.00c-V3.00k 0x0210:0x0211 2 E

DOCUMENT HISTORY Slave Controller – IP Core for Xilinx FPGAs III-III DOCUMENT HISTORY Version Comment 1.0  Initial release EtherCAT IP Core for

Features and Registers III-18 Slave Controller – IP Core for Xilinx FPGAs Address Length (Byte) Description IP Core V3.00c-V3.00k 0x0E08:0x0E0F 8 Ven

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-19 2.3 Extended ESC Features in User RAM Table 11: Extended ESC Features (R

Features and Registers III-20 Slave Controller – IP Core for Xilinx FPGAs Addr. Bit Feat. Description Reset Value 0F85 0 32 MI control by PDI possibl

Features and Registers Slave Controller – IP Core for Xilinx FPGAs III-21 Addr. Bit Feat. Description Reset Value 0F8A 0 72 Reserved 0 1 73 Reserve

Features and Registers III-22 Slave Controller – IP Core for Xilinx FPGAs Addr. Bit Feat. Description Reset Value 0F91 0 128 Reserved 0 1 129 Reserve

IP Core Installation Slave Controller – IP Core for Xilinx FPGAs III-23 3 IP Core Installation 3.1 Installation on Windows PCs 3.1.1 System Requ

IP Core Installation III-24 Slave Controller – IP Core for Xilinx FPGAs 3.2 Installation on Linux PCs 3.2.1 System Requirements The system requirem

IP Core Installation Slave Controller – IP Core for Xilinx FPGAs III-25 3.4 License File The license file for the EtherCAT IP Core (iptb_ethercat_

IP Core Installation III-26 Slave Controller – IP Core for Xilinx FPGAs 3.6 RSA Decryption Keys The Xilinx XST synthesis flow requires two decryptio

IP Core Installation Slave Controller – IP Core for Xilinx FPGAs III-27 3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow 3.8.1 Sof

CONTENTS III-IV Slave Controller – IP Core for Xilinx FPGAs CONTENTS 1 Overview 1 1.1 Frame processing order 2 1.2 Scope of this document 3 1.3

IP Core Usage III-28 Slave Controller – IP Core for Xilinx FPGAs 4 IP Core Usage 4.1 IPCore_Config Tool This chapter explains how to configure your

IP Core Usage Slave Controller – IP Core for Xilinx FPGAs III-29 - A VHDL package which contains the component declaration of the IP Core (pk_<

IP Core Usage III-30 Slave Controller – IP Core for Xilinx FPGAs 8. Now you can find your user configured EtherCAT IP Core in the IP Catalog for add

IP Core Usage Slave Controller – IP Core for Xilinx FPGAs III-31 Figure 9: EDK – Configuration Dialog 10. Assign addresses to the EtherCAT IP Core

IP Core Usage III-32 Slave Controller – IP Core for Xilinx FPGAs 11. The tab "Ports" in the "System Assembly View" shows the conn

IP Core Usage Slave Controller – IP Core for Xilinx FPGAs III-33 12. Generate Bitstream Result is the file "system.bit" in the implementa

IP Core Configuration III-34 Slave Controller – IP Core for Xilinx FPGAs 5 IP Core Configuration Figure 12: EtherCAT IP Core Configuration Interfac

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-35 5.1.1 Product ID tab Figure 13: Product ID tab PRODUCT_ID input in decim

IP Core Configuration III-36 Slave Controller – IP Core for Xilinx FPGAs 5.1.2 Physical Layer tab Figure 14: Physical Layer tab Communication Ports

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-37 Independent PHY addresses Enable if the PHY addresses are not consecutive.

CONTENTS Slave Controller – IP Core for Xilinx FPGAs III-V 5.1.2 Physical Layer tab 36 5.1.3 Internal Functions tab 38 5.1.4 Feature Details

IP Core Configuration III-38 Slave Controller – IP Core for Xilinx FPGAs 5.1.3 Internal Functions tab Figure 15: Internal Functions tab FMMUs Numb

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-39 Mapping to global IRQ Sync0 and Sync1 can additionally be mapped internall

IP Core Configuration III-40 Slave Controller – IP Core for Xilinx FPGAs 5.1.4 Feature Details tab Figure 16: Feature Details tab Read/Write Offset

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-41 PDI SM/IRQ acknowledge by WRITE Some ESC functions are triggered by readin

IP Core Configuration III-42 Slave Controller – IP Core for Xilinx FPGAs 5.1.5 Register: Process Data Interface tab Several interfaces between ESC

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-43 5.1.5.1 No Interface and General Purpose I/O If there is no interface sel

IP Core Configuration III-44 Slave Controller – IP Core for Xilinx FPGAs 5.1.5.2 Digital I/O Configuration The Digital I/O PDI supports up to 4 Byte

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-45 5.1.5.3 µController Configuration (8/16Bit) The 8/16 Bit µController inte

IP Core Configuration III-46 Slave Controller – IP Core for Xilinx FPGAs 5.1.5.4 SPI Configuration The SPI interface is a serial slave interface for

IP Core Configuration Slave Controller – IP Core for Xilinx FPGAs III-47 5.1.5.5 Processor Local Bus (PLB) Configuration The PLB v4.6 PDI connects

CONTENTS III-VI Slave Controller – IP Core for Xilinx FPGAs 9.1 PHY Management interface 78 9.1.1 PHY Management Interface Signals 78 9.1.2 PHY

IP Core Configuration III-48 Slave Controller – IP Core for Xilinx FPGAs 5.1.5.6 AXI4/AXI4 LITE Configuration The AXI PDI connects the IP Core with

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-49 6 Example Designs Example designs are available for:  Avnet Xilinx Spartan-6

Example Designs III-50 Slave Controller – IP Core for Xilinx FPGAs 6.1 Avnet Xilinx Spartan-6 LX150T Development Kit with Digital I/O 6.1.1 Configu

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-51 6.1.4 SII EEPROM Use this ESI for the SII EEPROM: Beckhoff Automation GmbH (Eva

Example Designs III-52 Slave Controller – IP Core for Xilinx FPGAs 6.2 Avnet Xilinx Spartan-6 LX150T Development Kit with AXI 6.2.1 Configuration a

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-53 6.2.3 Implementation 1. Open Xilinx EDK 2. Open project: <IPInst_dir>\

Example Designs III-54 Slave Controller – IP Core for Xilinx FPGAs 6.3 Xilinx Zynq ZC702 Development Kit with AXI (Vivado based) 6.3.1 Configuratio

Example Designs Slave Controller – IP Core for Xilinx FPGAs III-55 6.3.3 Implementation 1. Open Xilinx Vivado 2. Open project: <IPInst_dir&g

FPGA Resource Consumption III-56 Slave Controller – IP Core for Xilinx FPGAs 7 FPGA Resource Consumption The resource consumption figures shown in t

FPGA Resource Consumption Slave Controller – IP Core for Xilinx FPGAs III-57 Table 16: Approximate resource requirements for main configurable func

CONTENTS Slave Controller – IP Core for Xilinx FPGAs III-VII 10.3 Asynchronous 8/16 bit µController Interface 109 10.3.1 Interface 109 10.3.2

FPGA Resource Consumption III-58 Slave Controller – IP Core for Xilinx FPGAs The EtherCAT IP core resource consumption figures for typical EtherCAT d

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-59 8 IP Core Signals The available signals depend on the IP Core configuration. 8.

IP Core Signals III-60 Slave Controller – IP Core for Xilinx FPGAs 8.1.1 Clock source example schematics The EtherCAT IP Core and the Ethernet PHYs

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-61 8.2 SII EEPROM Interface Signals Table 19: SII EEPROM Signals Condition Name Di

IP Core Signals III-62 Slave Controller – IP Core for Xilinx FPGAs 8.4 Distributed Clocks SYNC/LATCH Signals Table 21 lists the signals used with Di

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-63 8.5 Physical Layer Interface The IP Core is connected with Ethernet PHYs using

IP Core Signals III-64 Slave Controller – IP Core for Xilinx FPGAs 8.5.1 MII Interface Table 23 lists the signals used with MII. The TX_CLK signals

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-65 Condition Name Direction Description Port2 = MII nMII_LINK2 INPUT 0: 100 Mbit/

IP Core Signals III-66 Slave Controller – IP Core for Xilinx FPGAs 8.5.2 RMII Interface Table 24 lists the signals used with RMII. Table 24: PHY Int

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-67 8.5.3 RGMII Interface Table 25 lists the signals used with RGMII. Table 25: PHY

TABLES III-VIII Slave Controller – IP Core for Xilinx FPGAs TABLES Table 1: IP Core Main Features ...

IP Core Signals III-68 Slave Controller – IP Core for Xilinx FPGAs Condition Name Direction Description Port1 = RGMII nRGMII_LINK1 INPUT 0: 100 Mbi

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-69 Condition Name Direction Description Port2 = RGMII nRGMII_LINK2 INPUT 0: 100 M

IP Core Signals III-70 Slave Controller – IP Core for Xilinx FPGAs 8.6 PDI Signals 8.6.1 General PDI Signals Table 27 lists the signals available i

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-71 8.6.3 SPI Slave Interface Table 28 used with an SPI PDI. Table 28: SPI PDI Cond

IP Core Signals III-72 Slave Controller – IP Core for Xilinx FPGAs 8.6.4.1 8 Bit µController Interface Table 30 lists the signals used with an 8 Bit

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-73 8.6.5 PLB Processor Local Bus Table 32 lists the signals used with the PLB v4.6

IP Core Signals III-74 Slave Controller – IP Core for Xilinx FPGAs Condi-tion Name Direction Description PDI_PLB_wrPendPri(0:1) INPUT PLB pending wri

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-75 Table 33: PLB PDI additional signals of XPS/EDK pcores Condition Name Direction

IP Core Signals III-76 Slave Controller – IP Core for Xilinx FPGAs 8.6.6 AXI4 / AXI4 LITE On-Chip Bus Table 34 lists the signals used with the AXI4

IP Core Signals Slave Controller – IP Core for Xilinx FPGAs III-77 Condition Name Direction Description AXI4 PDI_AXI_BID[PDI_BUS_ID_WIDTH-1:0] OUTP

TABLES Slave Controller – IP Core for Xilinx FPGAs III-IX Table 61: AXI4 LITE signals ...

Ethernet Interface III-78 Slave Controller – IP Core for Xilinx FPGAs 9 Ethernet Interface The IP Core is connected with Ethernet PHYs using MII, RM

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-79 9.1.3 Separate external MII management interfaces If two separate external M

Ethernet Interface III-80 Slave Controller – IP Core for Xilinx FPGAs 9.2 MII Interface The MII interface of the IP Core is optimized for low proces

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-81 9.2.1 MII Interface Signals The MII interface of the IP Core has the followi

Ethernet Interface III-82 Slave Controller – IP Core for Xilinx FPGAs 9.2.2 TX Shift Compensation Since IP Core and the Ethernet PHYs share the same

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-83 Table 39: MII TX Timing characteristics Parameter Comment tCLK25 25 MHz quart

Ethernet Interface III-84 Slave Controller – IP Core for Xilinx FPGAs 9.2.4 MII example schematic Refer to chapter 8.5.1 for more information on spe

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-85 9.3 RMII Interface The IP Core supports RMII with 2 communication ports. Nev

Ethernet Interface III-86 Slave Controller – IP Core for Xilinx FPGAs NOTE: A pull-down resistor is typically required for NPHY_RESET_OUT to hold the

Ethernet Interface Slave Controller – IP Core for Xilinx FPGAs III-87 9.4 RGMII Interface The IP Core supports RGMII with1-3 communication ports a