
IP Core Signals
III-76 Slave Controller – IP Core for Xilinx FPGAs
8.6.6 AXI4 / AXI4 LITE On-Chip Bus
Table 34 lists the signals used with the AXI4 and AXI4 LITE PDI.
Table 34: AXI4 / AXI4 LITE PDI
AXI data bus width
(8/16/32/64 bit)
AXI bus clock frequency in
Hz (>= 25,000)
AXI address width (>= 16
bit, only 16 bit are used)
PDI_AXI_WDATA
[PDI_EXT_BUS_WIDTH-1:0]
PDI_AXI_WSTRB
[PDI_EXT_BUS_WIDTH/8-1:0]
PDI_AXI_RDATA
[PDI_EXT_BUS_WIDTH-1:0]
PDI_AXI_AWID
[PDI_BUS_ID_WIDTH-1:0]
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