Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Instrukcja Użytkownika Pobierz pdf (Strona 7)

CONTENTS

Slave Controller – IP Core for Xilinx FPGAs III-VII

10.3 Asynchronous 8/16 bit µController Interface 109

10.3.1 Interface 109

10.3.2 Configuration 109

10.3.3 µController access 110

10.3.4 Write access 110

10.3.5 Read access 110

10.3.6 µController access errors 111

10.3.7 Connection with 16 bit µControllers without byte addressing 111

10.3.8 Connection with 8 bit µControllers 112

10.3.9 Timing Specification 113

10.4 PLB Slave Interface 117

10.4.1 Interface 117

10.4.2 Configuration 118

10.4.3 Timing specifications 119

10.5 AXI4/AXI4 LITE On-Chip Bus 121

10.5.1 Interface 121

10.5.2 Configuration 123

10.5.3 Interrupts 123

10.5.4 Timing specifications 124

11 Distributed Clocks SYNC/LATCH Signals 126

11.1 Signals 126

11.2 Timing specifications 126

12 SII EEPROM Interface (I²C) 127

12.1 Signals 127

12.2 EEPROM Emulation 127

12.3 Timing specifications 127

13 Electrical Specifications 128

14 Synthesis Constraints 129

15 Appendix 132

15.1 Support and Service 132

15.1.1 Beckhoff’s branch offices and representatives 132

15.2 Beckhoff Headquarters 132

1 2 3 4 5 6 7 8 9 10 11 12 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Instrukcja Użytkownika Strona 7