
Features and Registers
III-16 Slave Controller – IP Core for Xilinx FPGAs
2.2 Registers
An EtherCAT Slave Controller (ESC) has an address space of 64KByte. The first block of 4KByte
(0x0000:0x0FFF) is dedicated for registers. The process data RAM starts at address 0x1000, its size
is configurable.
Some registers are implemented depending on the configuration.
Table 9 gives an overview of the available registers.
Table 9: Register availability
Configured Station Address
Write Register Protection
Physical Read/Write Offset
DC Sync/Latch Configuration
Extended PDI Configuration
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