Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika

Version 1.0 Date: 2015-01-20 Hardware Data Sheet Section III ET1810 / ET1811 / ET1812 Slave Controller IP Core for Altera® FPGAs Release 3.0.10

FIGURES III-X Slave Controller – IP Core for Altera FPGAs FIGURES Figure 1: EtherCAT IP Core Block Diagram ...

PDI Description III-88 Slave Controller – IP Core for Altera FPGAs 10.1 Digital I/O Interface 10.1.1 Interface The Digital I/O PDI is selected with

PDI Description Slave Controller – IP Core for Altera FPGAs III-89 10.1.2 Configuration The Digital I/O interface is selected with PDI type 0x04 i

PDI Description III-90 Slave Controller – IP Core for Altera FPGAs 32Output registerDigital I/O output data register 0x0F00:0x0F03Watchdog&3232EO

PDI Description Slave Controller – IP Core for Altera FPGAs III-91 10.1.7 SOF SOF indicates the start of an Ethernet/EtherCAT frame. It is asserte

PDI Description III-92 Slave Controller – IP Core for Altera FPGAs SOFDATAInput DATAtSOF_to_DATA_setuptSOFtSOF_to_DATA_hold Figure 35: Digital Input:

PDI Description Slave Controller – IP Core for Altera FPGAs III-93 OUTVALIDDATAtDATA_to _OUTVALIDOutput DATAtOUTVALIDtOE_EXT_to _DATA_invalidOE_EXT

PDI Description III-94 Slave Controller – IP Core for Altera FPGAs 10.2 SPI Slave Interface 10.2.1 Interface An EtherCAT device with PDI type 0x05

PDI Description Slave Controller – IP Core for Altera FPGAs III-95 10.2.3 SPI access Each SPI access is separated into an address phase and a data

PDI Description III-96 Slave Controller – IP Core for Altera FPGAs 10.2.5 Commands The command CMD0 in the second address/command byte may be READ,

PDI Description Slave Controller – IP Core for Altera FPGAs III-97 10.2.8.1 Read Wait State Between the last address phase byte and the first data

FIGURES Slave Controller – IP Core for Altera FPGAs III-XI Figure 61: LatchSignal timing ...

PDI Description III-98 Slave Controller – IP Core for Altera FPGAs 10.2.10 2 Byte and 4 Byte SPI Masters Some SPI masters do not allow an arbitrary n

PDI Description Slave Controller – IP Core for Altera FPGAs III-99 10.2.11 Timing specifications Table 51: SPI timing characteristics IP Core Param

PDI Description III-100 Slave Controller – IP Core for Altera FPGAs Table 52: Read/Write timing diagram symbols Symbol Comment A15..A0 Address bits [

PDI Description Slave Controller – IP Core for Altera FPGAs III-101 C00SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late

PDI Description III-102 Slave Controller – IP Core for Altera FPGAs C00SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late s

PDI Description Slave Controller – IP Core for Altera FPGAs III-103 SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sa

PDI Description III-104 Slave Controller – IP Core for Altera FPGAs SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late samp

PDI Description Slave Controller – IP Core for Altera FPGAs III-105 10.3 Asynchronous 8/16 bit µController Interface 10.3.1 Interface The asynchr

PDI Description III-106 Slave Controller – IP Core for Altera FPGAs 10.3.3 µController access The 8 bit µController interface reads or writes 8 bit

PDI Description Slave Controller – IP Core for Altera FPGAs III-107 10.3.6 µController access errors These reasons for µController access errors a

ABBREVIATIONS III-XII Slave Controller – IP Core for Altera FPGAs ABBREVIATIONS µC Microcontroller ADR Address AL Application Layer AMBA® Advanced M

PDI Description III-108 Slave Controller – IP Core for Altera FPGAs 10.3.8 Connection with 8 bit µControllers If the ESC is connected to 8 bit µCont

PDI Description Slave Controller – IP Core for Altera FPGAs III-109 10.3.9 Timing Specification Table 56: µController timing characteristics IP Co

PDI Description III-110 Slave Controller – IP Core for Altera FPGAs Parameter Min Max Comment tBUSY_to_WR_CS 0 ns9 WR or CS deassertion after BUSY d

PDI Description Slave Controller – IP Core for Altera FPGAs III-111 BHE1CSBHEWRRDDATABUSYADR1ADRtWR_activetCS_delaytWR_delaytADR_BHE_DATA_holdDATA

PDI Description III-112 Slave Controller – IP Core for Altera FPGAs BHE1CSBHEWRRDDATABUSYADR1ADRtWR_activetCS_delaytWR_delaytADR_BHE_DATA_holdDATA1tA

PDI Description Slave Controller – IP Core for Altera FPGAs III-113 10.4 Avalon Slave Interface 10.4.1 Interface The Avalon Slave PDI is selected

PDI Description III-114 Slave Controller – IP Core for Altera FPGAs 10.4.2 Configuration The Avalon interface has PDI type 0x80 in the PDI control r

PDI Description Slave Controller – IP Core for Altera FPGAs III-115 10.4.5 Timing specifications Table 58: Avalon timing characteristics Parameter

PDI Description III-116 Slave Controller – IP Core for Altera FPGAs CLK_PDI_EXTADR/BEADRREADBUSYRD_DATADATAtReadCStClk Figure 54: Avalon Read Access

PDI Description Slave Controller – IP Core for Altera FPGAs III-117 10.5 AXI3 On-Chip Bus 10.5.1 Interface The AXI3 Slave PDI is selected during

Overview Slave Controller – IP Core for Altera FPGAs III-1 1 Overview The EtherCAT IP Core is a configurable EtherCAT Slave Controller (ESC). It t

PDI Description III-118 Slave Controller – IP Core for Altera FPGAs Signal Direction Description Channel Signal polarity PDI_AXI_WLAST IN Write data

PDI Description Slave Controller – IP Core for Altera FPGAs III-119 10.5.2 Configuration The AXI3 interface has PDI type 0x80 in the PDI control r

PDI Description III-120 Slave Controller – IP Core for Altera FPGAs 10.5.4 Timing specifications The AXI PDI accepts read and write accesses simulta

PDI Description Slave Controller – IP Core for Altera FPGAs III-121 CLK_PDI_EXTARREADYADRARADRRVALIDRDATADATAtReadARVALIDtClk Figure 58: AXI Read A

Distributed Clocks SYNC/LATCH Signals III-122 Slave Controller – IP Core for Altera FPGAs 11 Distributed Clocks SYNC/LATCH Signals For details about

SII EEPROM Interface (I²C) Slave Controller – IP Core for Altera FPGAs III-123 12 SII EEPROM Interface (I²C) For details about the ESC SII EEPROM

Electrical Specifications III-124 Slave Controller – IP Core for Altera FPGAs 13 Electrical Specifications Table 65: AC Characteristics Symbol Param

Synthesis Constraints Slave Controller – IP Core for Altera FPGAs III-125 14 Synthesis Constraints The EtherCAT IP Core contains true dual-port me

Synthesis Constraints III-126 Slave Controller – IP Core for Altera FPGAs Signal Requirement Value Clock reference Description RGMII_TX_CTL0-3 RGMII_

Synthesis Constraints Slave Controller – IP Core for Altera FPGAs III-127 Example Design Constraints File (SDC) ## Constraints for EL9800_DIGI_EP3C

Overview III-2 Slave Controller – IP Core for Altera FPGAs 1.1 Frame processing order The frame processing order of the EtherCAT IP Core is as follo

Synthesis Constraints III-128 Slave Controller – IP Core for Altera FPGAs set_false_path -from [get_clocks {DIGI_CLK}] -to [get_clocks {PLL_INST|altp

Appendix Slave Controller – IP Core for Altera FPGAs III-129 15 Appendix 15.1 Support and Service Beckhoff and our partners around the world offe

Overview Slave Controller – IP Core for Altera FPGAs III-3 1.2 Scope of this document Purpose of this document is to describe the installation and

Overview III-4 Slave Controller – IP Core for Altera FPGAs 1.4 Target FPGAs The EtherCAT IP Core for Altera® FPGAs is targeted at these FPGA familie

Overview Slave Controller – IP Core for Altera FPGAs III-5 1.6 Tested FPGA/Designflow combinations The EtherCAT IP Core has been synthesized succe

Overview III-6 Slave Controller – IP Core for Altera FPGAs 1.7 Release Notes EtherCAT IP Core updates deliver feature enhancements and removed restr

Overview Slave Controller – IP Core for Altera FPGAs III-7 Version Release notes which is typically true for AXI4LITE.  The AXI PDI may read addi

DOCUMENT ORGANIZATION III-II Slave Controller – IP Core for Altera FPGAs DOCUMENT ORGANIZATION The Beckhoff EtherCAT Slave Controller (ESC) documenta

Overview III-8 Slave Controller – IP Core for Altera FPGAs Version Release notes 3.0.2 (5/2013) Enhancements:  MI link detection: relaxed checking

Overview Slave Controller – IP Core for Altera FPGAs III-9 Version Release notes 3.0.5 (2/2014) Enhancements:  Improved MegaWizard GUI: shows on-

Overview III-10 Slave Controller – IP Core for Altera FPGAs Version Release notes 3.0.6 (4/2014) Enhancements:  The Sync/Latch PDI Configuration re

Overview Slave Controller – IP Core for Altera FPGAs III-11 Version Release notes 3.0.10 (1/2015) The EL9800/FB1122 example designs have been remov

Overview III-12 Slave Controller – IP Core for Altera FPGAs 1.7.1 Major differences between V2.4.x and V3.0.x The EtherCAT IP Core V3.0.x versions h

Overview Slave Controller – IP Core for Altera FPGAs III-13 1.8 Design flow The design flow for creating an EtherCAT Slave Controller based on the

Overview III-14 Slave Controller – IP Core for Altera FPGAs 1.9 OpenCore Plus Evaluation The EtherCAT IP Core for Altera FPGAs supports OpenCore Plu

Overview Slave Controller – IP Core for Altera FPGAs III-15 1.10 Simulation A behavioral simulation model of the EtherCAT IP core is not available

Features and Registers III-16 Slave Controller – IP Core for Altera FPGAs 2 Features and Registers 2.1 Features Table 7: IP Core Feature DetailsFea

Features and Registers Slave Controller – IP Core for Altera FPGAs III-17 Feature IP Core Altera® V3.0.10 IP Core Altera® V3.0.0-3.0.9 Wait State

DOCUMENT HISTORY Slave Controller – IP Core for Altera FPGAs III-III DOCUMENT HISTORY Version Comment 1.0  Initial release EtherCAT IP Core for A

Features and Registers III-18 Slave Controller – IP Core for Altera FPGAs Feature IP Core Altera® V3.0.10 IP Core Altera® V3.0.0-3.0.9 Propagation

Features and Registers Slave Controller – IP Core for Altera FPGAs III-19 2.2 Registers An EtherCAT Slave Controller (ESC) has an address space of

Features and Registers III-20 Slave Controller – IP Core for Altera FPGAs Address Length (Byte) Description IP Core V3.0.0-V3.0.10 0x0210:0x0211 2 EC

Features and Registers Slave Controller – IP Core for Altera FPGAs III-21 Address Length (Byte) Description IP Core V3.0.0-V3.0.10 0x0E08:0x0E0F 8

Features and Registers III-22 Slave Controller – IP Core for Altera FPGAs 2.3 Extended ESC Features in User RAM Table 11: Extended ESC Features (Res

Features and Registers Slave Controller – IP Core for Altera FPGAs III-23 Addr. Bit Feat. Description Reset Value 0F85 0 32 MI control by PDI possi

Features and Registers III-24 Slave Controller – IP Core for Altera FPGAs Addr. Bit Feat. Description Reset Value 0F8A 0 72 Reserved 0 1 73 Reserved

Features and Registers Slave Controller – IP Core for Altera FPGAs III-25 Addr. Bit Feat. Description Reset Value 0F91 0 128 Reserved 0 1 129 Reser

IP Core Installation III-26 Slave Controller – IP Core for Altera FPGAs 3 IP Core Installation 3.1 Installation on Windows PCs 3.1.1 System Requir

IP Core Installation Slave Controller – IP Core for Altera FPGAs III-27 3.2 Installation on Linux PCs 3.2.1 System Requirements The system requir

CONTENTS III-IV Slave Controller – IP Core for Altera FPGAs CONTENTS 1 Overview 1 1.1 Frame processing order 2 1.2 Scope of this document 3 1.3

IP Core Installation III-28 Slave Controller – IP Core for Altera FPGAs 3.4 License File The license file for the EtherCAT IP Core (license_<comp

IP Core Installation Slave Controller – IP Core for Altera FPGAs III-29 3.5 IP Core Vendor ID package The Vendor ID Package (VHDL file) is part of

IP Core Installation III-30 Slave Controller – IP Core for Altera FPGAs 3.6 Integrating the EtherCAT IP Core into the Altera Designflow Quartus II e

IP Core Usage Slave Controller – IP Core for Altera FPGAs III-31 4 IP Core Usage 4.1 IP Catalog The EtherCAT IP Core is integrated in the Quartus

IP Core Configuration III-32 Slave Controller – IP Core for Altera FPGAs 5 IP Core Configuration Figure 7: EtherCAT IP Core Configuration Interface

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-33 5.1 Documentation Figure 8: Documentation General information Name and

IP Core Configuration III-34 Slave Controller – IP Core for Altera FPGAs 5.2 Parameters 5.2.1 Product ID tab Figure 9: Product ID tab PRODUCT_ID i

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-35 5.2.2 Physical Layer tab Figure 10: Physical Layer tab Communication Por

IP Core Configuration III-36 Slave Controller – IP Core for Altera FPGAs PHY Management Interface The PHY Management Interface function can be select

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-37 5.2.3 Internal Functions tab Figure 11: Internal Functions tab FMMUs Nu

CONTENTS Slave Controller – IP Core for Altera FPGAs III-V 5.2.4 Feature Details tab 39 5.2.5 Process Data Interface tab 41 6 Example Designs

IP Core Configuration III-38 Slave Controller – IP Core for Altera FPGAs Distributed Clocks enabled The Distributed Clocks feature comprises synchron

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-39 5.2.4 Feature Details tab Figure 12: Feature Details tab Read/Write Offs

IP Core Configuration III-40 Slave Controller – IP Core for Altera FPGAs PDI information register PDI information register 0x014E:0x014F is available

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-41 5.2.5 Process Data Interface tab Several interfaces between ESC and the a

IP Core Configuration III-42 Slave Controller – IP Core for Altera FPGAs 5.2.5.1 No Interface and General Purpose I/O If there is no interface selec

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-43 5.2.5.2 Digital I/O Configuration The Digital I/O PDI supports up to 4 By

IP Core Configuration III-44 Slave Controller – IP Core for Altera FPGAs Output Mode Defines the trigger signal for data output.  Output at EOF (En

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-45 5.2.5.3 µController Configuration (8/16Bit) The 8/16 Bit µController inte

IP Core Configuration III-46 Slave Controller – IP Core for Altera FPGAs 5.2.5.4 SPI Configuration The SPI interface is a serial slave interface for

IP Core Configuration Slave Controller – IP Core for Altera FPGAs III-47 5.2.5.5 Avalon Configuration The Avalon PDI connects the IP Core with an

CONTENTS III-VI Slave Controller – IP Core for Altera FPGAs 8.6.5 Avalon On-Chip Bus 72 8.6.6 AXI3 On-Chip Bus 73 9 Ethernet Interface 74 9.1

IP Core Configuration III-48 Slave Controller – IP Core for Altera FPGAs 5.2.5.6 AXI3 Configuration The AXI3 PDI connects the IP Core with an AXI Ma

Example Designs Slave Controller – IP Core for Altera FPGAs III-49 6 Example Designs Example designs are available for:  EBV Cyclone III Evaluat

Example Designs III-50 Slave Controller – IP Core for Altera FPGAs 6.1 EBV Cyclone III DBC3C40 with Digital I/O 6.1.1 Configuration and resource co

Example Designs Slave Controller – IP Core for Altera FPGAs III-51 6.1.5 Downloadable configuration file An already synthesized time limited OpenC

Example Designs III-52 Slave Controller – IP Core for Altera FPGAs 6.2 EBV Cyclone IV DBC4CE55 with NIOS 6.2.1 Configuration and resource consumpti

Example Designs Slave Controller – IP Core for Altera FPGAs III-53 14. Switch over to Quartus II window 15. Select menu “Project – Add/Remove Files

Example Designs III-54 Slave Controller – IP Core for Altera FPGAs 6.3 Altera Cyclone IV DE2-115 with NIOS and MII 6.3.1 Configuration and resource

Example Designs Slave Controller – IP Core for Altera FPGAs III-55 6.3.3 Implementation The SOPC needs to be generated before implementing the exa

Example Designs III-56 Slave Controller – IP Core for Altera FPGAs 6.4 Altera Cyclone IV DE2-115 with NIOS and RGMII 6.4.1 Configuration and resour

FPGA Resource Consumption Slave Controller – IP Core for Altera FPGAs III-57 7 FPGA Resource Consumption The resource consumption figures shown in

CONTENTS Slave Controller – IP Core for Altera FPGAs III-VII 10.2.9 SPI access errors and SPI status flag 97 10.2.10 2 Byte and 4 Byte SPI Maste

FPGA Resource Consumption III-58 Slave Controller – IP Core for Altera FPGAs The EtherCAT IP core resource consumption figures for typical EtherCAT d

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-59 8 IP Core Signals The available signals depend on the IP Core configuration. 8.

IP Core Signals III-60 Slave Controller – IP Core for Altera FPGAs 8.1.1 Clock source example schematics The EtherCAT IP Core and the Ethernet PHYs

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-61 8.2 SII EEPROM Interface Signals Table 20: SII EEPROM Signals Condition Name Di

IP Core Signals III-62 Slave Controller – IP Core for Altera FPGAs 8.4 Distributed Clocks SYNC/LATCH Signals Table 22 lists the signals used with Di

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-63 8.5 Physical Layer Interface The IP Core is connected with Ethernet PHYs using

IP Core Signals III-64 Slave Controller – IP Core for Altera FPGAs 8.5.1 MII Interface Table 24 lists the signals used with MII. The TX_CLK signals

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-65 Condition Name Direction Description Port2 = MII nMII_LINK2 INPUT 0: 100 Mbit/

IP Core Signals III-66 Slave Controller – IP Core for Altera FPGAs 8.5.2 RMII Interface Table 25 lists the signals used with RMII. Table 25: PHY Int

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-67 8.5.3 RGMII Interface Table 26 lists the signals used with RGMII. Table 26: PHY

TABLES III-VIII Slave Controller – IP Core for Altera FPGAs TABLES Table 1: IP Core Main Features ...

IP Core Signals III-68 Slave Controller – IP Core for Altera FPGAs Condition Name Direction Description Port1 = RGMII nRGMII_LINK1 INPUT 0: 100 Mbi

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-69 Condition Name Direction Description Port2 = RGMII nRGMII_LINK2 INPUT 0: 100 M

IP Core Signals III-70 Slave Controller – IP Core for Altera FPGAs 8.6 PDI Signals 8.6.1 General PDI Signals Table 28 lists the signals available i

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-71 8.6.3 SPI Slave Interface Table 29 used with an SPI PDI. Table 29: SPI PDI Cond

IP Core Signals III-72 Slave Controller – IP Core for Altera FPGAs 8.6.4.2 16 Bit µController Interface Table 32 lists the signals used with a 16 Bi

IP Core Signals Slave Controller – IP Core for Altera FPGAs III-73 8.6.6 AXI3 On-Chip Bus Table 34 lists the signals used with the AXI3 PDI. Tabl

Ethernet Interface III-74 Slave Controller – IP Core for Altera FPGAs 9 Ethernet Interface The IP Core is connected with Ethernet PHYs using MII, RM

Ethernet Interface Slave Controller – IP Core for Altera FPGAs III-75 9.1.3 Separate external MII management interfaces If two separate external M

Ethernet Interface III-76 Slave Controller – IP Core for Altera FPGAs 9.2 MII Interface The MII interface of the IP Core is optimized for low proces

Ethernet Interface Slave Controller – IP Core for Altera FPGAs III-77 9.2.1 MII Interface Signals The MII interface of the IP Core has the followi

TABLES Slave Controller – IP Core for Altera FPGAs III-IX Table 61: Distributed Clocks signals ...

Ethernet Interface III-78 Slave Controller – IP Core for Altera FPGAs 9.2.2 TX Shift Compensation Since IP Core and the Ethernet PHYs share the same

Ethernet Interface Slave Controller – IP Core for Altera FPGAs III-79 Table 38: MII TX Timing characteristics Parameter Comment tCLK25 25 MHz quart

Ethernet Interface III-80 Slave Controller – IP Core for Altera FPGAs 9.2.4 MII example schematic Refer to chapter 8.5 for more information on speci

Ethernet Interface Slave Controller – IP Core for Altera FPGAs III-81 9.3 RMII Interface The IP Core supports RMII with 2 communication ports. Nev

Ethernet Interface III-82 Slave Controller – IP Core for Altera FPGAs Table 40: RMII Interface signals Signal Direction Description CLK50 IN RMII RX/

Ethernet Interface Slave Controller – IP Core for Altera FPGAs III-83 9.4 RGMII Interface The IP Core supports RGMII with1-3 communication ports a

Ethernet Interface III-84 Slave Controller – IP Core for Altera FPGAs EtherCAT devicenRGMII_LINKCLK25_2NSRGMII_RX_CLKRGMII_RX_CTL_DATA_DDR_NRESETRGMI

Ethernet Interface Slave Controller – IP Core for Altera FPGAs III-85 9.4.2 RGMII example schematic Refer to chapter 8.5 for more information on s

Ethernet Interface III-86 Slave Controller – IP Core for Altera FPGAs 9.4.4.1 TX_CLK Delay in PHY Some PHYs offer RGMII-ID, which means, the TX_CLK

PDI Description Slave Controller – IP Core for Altera FPGAs III-87 10 PDI Description Table 42: Available PDIs for EtherCAT IP Core PDI number 0x0