Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Pobierz pdf (Strona 12)

ABBREVIATIONS

III-XII Slave Controller – IP Core for Altera FPGAs

ABBREVIATIONS

µC

Microcontroller

ADR

Address

Application Layer

AMBA

Advanced Microcontroller Bus Architecture from ARM

AXI

Advanced eXtensible Interface Bus, an AMBA interconnect. Used as On-Chip-bus

BHE

Bus High Enable

CMD

Command

Chip Select

Distributed Clock

Data Link Layer

ECAT

EtherCAT

ESI

EtherCAT Slave Information

EOF

End of Frame

ESC

EtherCAT Slave Controller

FMMU

Fieldbus Memory Management Unit

FPGA

Field Programmable Gate Array

GPI

General Purpose Input

GPO

General Purpose Output

HDL

Hardware Description Language

Intellectual Property

IRQ

Interrupt Request

Logic Cell

Logic Element

MAC

Media Access Controller

MDIO

Management Data Input / Output

(PHY) Management Interface

MII

Media Independent Interface

MISO

Master In – Slave Out

MOSI

Master Out – Slave In

PDI

Process Data Interface

PLD

Programmable Logic Device

PLL

Phase Locked Loop

RBF

Raw Binary File

Read

RMII

Reduced Media Independent Interface

SyncManager

SoC

System on a Chip

SOF

Start of Frame

SOPC

System on a programmable Chip

SPI

Serial Peripheral Interface

VHDL

Very High Speed Integrated Circuit Hardware Description Language

Write

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Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Strona 12

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