Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Pobierz pdf (Strona 24)

Overview

III-12 Slave Controller – IP Core for Altera FPGAs

1.7.1 Major differences between V2.4.x and V3.0.x

The EtherCAT IP Core V3.0.x versions have these advantages compared with the V2.4.x versions:

 Increased PDI performance (average latency internally at least by a factor of 2 faster; worst case

latency even better)

 Support for 8/16/32/64 bit Avalon and AXI3

interface

 Support for RGMII ports

 Native support for FX PHYs

 Flexible PHY address configuration

 Support for PDI SyncManager/IRQ acknowledge by Write command (required for wide on-chip-

busses)

 More detailed configuration

The higher PDI performance increases the resource requirements of the V3.0.x versions compared

with the V2.4.x versions. New development is focused on the V3.0.x versions.

1.7.2 Reading IP Core version from device

The IP Core version, denoted as X.Y.Z (e.g., 2.4.0), consists of three values X, Y, and Z. These

values can be read out in registers 0x0001 and 0x0002.

Table 5: Register Revision (0x0001)

Bit

Description

ECAT

PDI

Reset Value

7:0

IP Core major version X

r/-

IP Core dep.

Table 6: Register Build (0x0002:0x0003)

Bit

Description

ECAT

PDI

Reset Value

3:0

IP Core maintenance version Z

r/-

IP Core dep.

7:4

IP Core minor version Y

r/-

IP Core dep.

15:8

Patch level:

0x00: original release

0x01-0x0F: patch level of original release

r/-

IP Core dep.

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 140 141

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