
Features and Registers
Slave Controller – IP Core for Altera FPGAs III-17
Number of address extension
byte(s)
2/4 Byte SPI master support
Extended error detection (read
busy violation)
Asynchronous µController PDI
Extended µC configuration bits
0x0150[7:4], 0x0152:0x0153
ADR[15:13] available (000
b
if not
available)
RD polarity configurable
(0x0150.7)
Read BUSY delay (0x0152.0)
Write after first edge (0x0152.2)
Synchronous µController PDI
Bus clock [MHz] (N=1,2,3,…)
DC SyncSignals available directly
and as IRQ
Bus clock multiplier in register
0x0150[6:0]
EtherCAT Bridge (port 3, EBUS/MII)
GPIO available independent of
PDI or port configuration
GPIO available without PDI
Concurrent access to GPO by
ECAT and PDI
Basic Information
(0x0000:0x0006)
ESC Features supported
(0x0008:0x0009)
Extended ESC Feature
Availability in User RAM (0x0F80
ff.)
Write Protection (0x0020:0x0031)
ESC DL Control (0x0100:0x0103)
bytes
EtherCAT only mode (0x0100.0)
Temporary loop control
(0x0100.1)
FIFO Size configurable
(0x0100[18:16])
Configured Station Address
(0x0010:0x0011)
Configured Station Alias
(0x0100.24, 0x0012:0x0013)
Physical Read/Write Offset
(0x0108:0x0109)
Application Layer Features
Extended AL Control/Status bits
(0x0120[15:5], 0x0130[15:5])
AL Status Emulation (0x0140.8)
AL Status Code (0x0134:0x0135)
ECAT Event Mask
(0x0200:0x0201)
AL Event Mask (0x0204:0x0207)
ECAT Event Request
(0x0210:0x0211)
AL Event Request
(0x0220:0x0223)
SyncManager activation changed
(0x0220.4)
SyncManager watchdog
expiration (0x0220.6)
RX Error Counter
(0x0300:0x0307)
Forwarded RX Error Counter
(0x0308:0x030B)
ECAT Processing Unit Error
Counter (0x030C)
PDI Error Counter (0x030D)
Lost Link Counter
(0x0310:0x0313)
Watchdog Divider configurable
(0x0400:0x0401)
Watchdog Counter Process Data
(0x0442)
Watchdog Counter PDI (0x0443)
SII EEPROM Interface (0x0500:0x050F)
EEPROM size reflected in
0x0502.7
EEPROM controllable by PDI
EEPROM Emulation CRC error
0x0502[11] PDI writable
Read data bytes (0x0502.6)
Internal Pull-Ups for
EEPROM_CLK and
EEPROM_DATA
Watchdog trigger generation for 1
Byte Mailbox configuration
independent of reading access
SyncManager Event Times
(+0x8[7:6])
4
(0-2 Sync-
Signals,
0- 2
Latch-
Signals)
4
(0-2 Sync-
Signals,
0- 2
Latch-
Signals)
SyncManager Event Times
(0x09F0:0x09FF)
DC Time Loop Control
controllable by PDI
DC activation by EEPROM
(0x0140[11:10])
Komentarze do niniejszej Instrukcji