Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Pobierz pdf (Strona 71)

IP Core Signals

Slave Controller – IP Core for Altera FPGAs III-59

8 IP Core Signals

The available signals depend on the IP Core configuration.

8.1 General Signals

Table 19: General Signals

Condition

Name

Direction

Description

nRESET

INPUT

Resets all registers of the

IP Core, active low

Reset slave by

ECAT/PDI

RESET_OUT

OUTPUT

Reset by ECAT (reset

high. RESET_OUT has to

trigger nRESET, which

clears RESET_OUT.

CLK25

INPUT

25 MHz clock signal from

PLL (rising edge

synchronous with rising

edge of CLK100)

CLK100

INPUT

100 MHz clock signal from

PLL

1 2 ... 66 67 68 69 70 71 72 73 74 75 76 ... 140 141

® FPGAs 1
1 Overview 13
EtherCAT IP Core 14
Table 4: Release notes 18
Figure 3: Design flow 25
2 Features and Registers 28
(0x0108:0x0109) 29
Table 8: Legend 30
IP Core 31
V3.0.10 31
Table 10: Legend 33
3 IP Core Installation 38
Figure 5: License Setup 40
4 IP Core Usage 43
5 IP Core Configuration 44
Figure 8: Documentation 45
Figure 9: Product ID tab 46
09) is available if checked 51
6 Example Designs 61
7 FPGA Resource Consumption 69
8 IP Core Signals 71
CLK25_2NS 72
Table 20: SII EEPROM Signals 73
Table 21: LED Signals 73
PHY Management 75
Table 24: PHY Interface MII 76
Table 25: PHY Interface RMII 78
Table 28: Digital I/O PDI 82
Table 29: SPI PDI 83
Table 30: 8/16 Bit µC PDI 83
Table 31: 8 Bit µC PDI 83
Table 32: 16 Bit µC PDI 84
Table 33: Avalon PDI 84
Table 34: AXI3 PDI 85
9 Ethernet Interface 86
Ethernet PHY 87
RX_D[3:0] 91
10 PDI Description 99
Digital output pins 102
LATCH_IN 104
Figure 39: OUT_ENA timing 105
Table 46: SPI signals 106
Table 47: Address modes 107
SPI_DO (MISO) 112
SPI_DI (MOSI) 112
SPI_CLK* 112
SPI mode 1/3 SPI mode 0/2 113
PDI Description 114
16 bit µController, async 119
EtherCAT device 119
8 bit µController, async 120
(with preceding write access) 122
DATA0 DATA1 DATA2 DATA3 128
ADR+1 ADR+3ADR+2 128
Figure 57: AXI3 signals 129
Table 59: AXI3 signals 129
Figure 58: AXI Read Access 133
Figure 59: AXI Write Access 133
Output event time 134
Table 63: I²C EEPROM signals 135
Table 65: AC Characteristics 136
Table 66: Forwarding Delays 136
14 Synthesis Constraints 137
Synthesis Constraints 138
Synthesis Constraints 139
15 Appendix 141

Komentarze do niniejszej Instrukcji

Brak uwag

Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Strona 71

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Ekwipunek Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10