
PDI Description
Slave Controller – IP Core for Altera FPGAs III-113
10.4 Avalon Slave Interface
10.4.1 Interface
The Avalon Slave PDI is selected during the IP Core configuration. It uses memory
addressing/dynamic bus sizing. The signals of the Avalon interface are:
EtherCAT
IP core
CLK_PDI_EXT
PDI_AVALON_READ
PDI_AVALON_WRITE
PDI_AVALON_RD_DATA
PDI_AVALON_WR_DATA
PDI_AVALON_IRQ
PDI_AVALON_ADR
PDI_AVALON_BUSY
PDI_AVALON_CS
PDI_AVALON_SYNC0/1
PDI_AVALON_BE
Figure 53: Avalon signals
Table 57: Avalon signals
PDI_AVALON_ADR
[18-ld(PDI_EXT_BUS_WIDTH):0]
PDI_AVALON_BE
[PDI_EXT_BUS_WIDTH/8-1:0]
PDI_AVALON_RD_DATA
[PDI_EXT_BUS_WIDTH-1:0]
PDI_AVALON_WR_DATA
[PDI_EXT_BUS_WIDTH-1:0]
DC Sync0/1 used as
interrupts
Please refer to the Avalon Memory-Mapped Interface Specification from Altera for details about the
Avalon bus (http://www.altera.com).
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