Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Pobierz pdf (Strona 9)

TABLES

Slave Controller – IP Core for Altera FPGAs III-IX

Table 61: Distributed Clocks signals ................................................................................................... 122

Table 62: DC SYNC/LATCH timing characteristics IP Core ............................................................... 122

Table 63: I²C EEPROM signals ........................................................................................................... 123

Table 64: EEPROM timing characteristics IP Core ............................................................................. 123

Table 65: AC Characteristics ............................................................................................................... 124

Table 66: Forwarding Delays ............................................................................................................... 124

Table 67: EtherCAT IP Core constraints ............................................................................................. 125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 140 141

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Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Strona 9