
IP Core Signals
Slave Controller – IP Core for Altera FPGAs III-61
8.2 SII EEPROM Interface Signals
Table 20: SII EEPROM Signals
0: up to 16 kbit EEPROM
1: 32 kbit-4Mbit EEPROM
Tristate drivers inside
core (EEPROM/MI)
EEPROM I²C Clock
(output values: 0 or Z)
External tristate drivers
for EEPROM/MI
Tristate drivers inside
core (EEPROM/MI)
External tristate drivers
for EEPROM/MI
EEPROM I²C Data:
EEPROM IP Core
EEPROM I²C Data :
IP Core EEPROM
(always 0)
0: disable output driver for
PROM_DATA_OUT
1: enable output driver for
PROM_DATA_OUT
8.3 LED Signals
Table 21 lists the signals used for the LEDs. The LED signals are active high. All LEDs should be
green.
Table 21: LED Signals
Link/activity LED for
ethernet port 0
2 or 3 communication
ports
Link/activity LED for
ethernet port 1
Link/activity LED for
Ethernet port 2
RUN LED for device status
Always 0 if RUN LED is
deactivated.
RUN_LED enabled and
Extended RUN/ERR
LED enabled
ERR LED for device
status.
Connect to RUN pin of
dual-color STATE LED,
connect LED_ERR to ERR
pin of STATE LED
NOTE: The application ERR LED and STATE LED can alternatively be controlled by a µController if required.
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