Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Instrukcja Użytkownika Strona 110
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PDI Description
III-98 Slave Controller – IP Core for Altera FPGAs
10.2.10 2 Byte and 4 Byte SPI Masters
Some SPI masters do not allow an arbitrary number of bytes per access, the number of bytes per
access must be a multiple of 2 or 4 (maybe even more). The SPI slave interface supports such
masters. The length of the data phase is in control of the master and can be set to the appropriate
length, the length of the address phase has to be extended. The address phase of a read access can
be set to a multiple of 2/4 by using the 3 byte address mode and a wait state byte. The address phase
of a write access can be enhanced to 4 bytes using 3 byte address mode and an additional address
extension byte (byte 2) according to Table 50.
Table 50: Write access for 2 and 4 Byte SPI Masters
Byte
2 Byte SPI master
4 Byte SPI master
0
A[12:5] address bits [12:5]
A[12:5] address bits [12:5]
1
A[4:0] address bits [4:0]
CMD0[2:0] write command: 100b
A[4:0] address bits [4:0]
CMD0[2:0] 3 byte addressing: 110b
2
D0[7:0] data byte 0
A[15:13] address bits [15:13]
CMD1[2:0] 3 byte addressing: 110b
res[1:0] two reserved bits, set to 00b
3
D1[7:0] data byte 1
A[15:13] address bits [15:13]
CMD2[2:0] write command: 100b
res[1:0] two reserved bits, set to 00b
4
D2[7:0] data byte 2
D0[7:0] data byte 0
5
D3[7:0] data byte 3
D1[7:0] data byte 1
6
D4[7:0] data byte 4
D2[7:0] data byte 2
7
D5[7:0] data byte 5
D3[7:0] data byte 3
NOTE: The address phase of a write access can be further extended by an arbitrary number of address extension
bytes containing 110b as the command. The address phase of a read access can also be enhanced with
additional address extension bytes (the read wait state has to be maintained anyway). The address portion of the
last address extension byte is used for the access.
- ® FPGAs 1
- 1 Overview 13
- EtherCAT IP Core 14
- Table 4: Release notes 18
- Figure 3: Design flow 25
- 2 Features and Registers 28
- (0x0108:0x0109) 29
- Table 8: Legend 30
- IP Core 31
- V3.0.10 31
- Table 10: Legend 33
- 3 IP Core Installation 38
- Figure 5: License Setup 40
- 4 IP Core Usage 43
- 5 IP Core Configuration 44
- Figure 8: Documentation 45
- Figure 9: Product ID tab 46
- 09) is available if checked 51
- 6 Example Designs 61
- 7 FPGA Resource Consumption 69
- 8 IP Core Signals 71
- CLK25_2NS 72
- Table 20: SII EEPROM Signals 73
- Table 21: LED Signals 73
- PHY Management 75
- Table 24: PHY Interface MII 76
- Table 25: PHY Interface RMII 78
- Table 28: Digital I/O PDI 82
- Table 29: SPI PDI 83
- Table 30: 8/16 Bit µC PDI 83
- Table 31: 8 Bit µC PDI 83
- Table 32: 16 Bit µC PDI 84
- Table 33: Avalon PDI 84
- Table 34: AXI3 PDI 85
- 9 Ethernet Interface 86
- Ethernet PHY 87
- RX_D[3:0] 91
- 10 PDI Description 99
- Digital output pins 102
- LATCH_IN 104
- Figure 39: OUT_ENA timing 105
- Table 46: SPI signals 106
- Table 47: Address modes 107
- SPI_DO (MISO) 112
- SPI_DI (MOSI) 112
- SPI_CLK* 112
- SPI mode 1/3 SPI mode 0/2 113
- PDI Description 114
- 16 bit µController, async 119
- EtherCAT device 119
- 8 bit µController, async 120
- (with preceding write access) 122
- DATA0 DATA1 DATA2 DATA3 128
- ADR+1 ADR+3ADR+2 128
- Figure 57: AXI3 signals 129
- Table 59: AXI3 signals 129
- Figure 58: AXI Read Access 133
- Figure 59: AXI Write Access 133
- Output event time 134
- Table 63: I²C EEPROM signals 135
- Table 65: AC Characteristics 136
- Table 66: Forwarding Delays 136
- 14 Synthesis Constraints 137
- Synthesis Constraints 138
- Synthesis Constraints 139
- 15 Appendix 141
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