Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Instrukcja Użytkownika Pobierz pdf (Strona 19)

Overview

Slave Controller – IP Core for Xilinx FPGAs III-7

The IP Core version, denoted as X.Yz (e.g., 1.00a), consists of three values X, Y, and z. These values

can be read out in registers 0x0001 and 0x0002. Value z is encoded like this: a=0, b=1, c=2, etc. .

Table 5: Register Revision (0x0001)

Bit

Description

ECAT

PDI

Reset Value

7:0

IP Core major version X

r/-

r/-

IP Core dep.

Table 6: Register Build (0x0002:0x0003)

Bit

Description

ECAT

PDI

Reset Value

3:0

IP Core maintenance version z

r/-

r/-

IP Core dep.

7:4

IP Core minor version Y

r/-

r/-

IP Core dep.

15:8

Patch level:

0x00: original release

0x01-0x0F: patch level of original release

r/-

r/-

IP Core dep.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 125 126

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