Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Instrukcja Użytkownika Pobierz pdf (Strona 92)

PDI Description

III-80 Slave Controller – IP Core for Xilinx FPGAs

SOF

DATA

Input DATA

SOF_to_DATA_setup

SOF

SOF_to_DATA_hold

Figure 36: Digital Input: Input data sampled at SOF, I/O can be read in the same frame

LATCH_IN

DATA

Input DATA

DATA_hold

DATA_setup

LATCH_IN

Input_event_delay

Figure 37: Digital Input: Input data sampled with LATCH_IN

OUTVALID

DATA

DATA_to_OUTVALID

Output DATA

OUTVALID

Zero or High-Impedance

OE_EXT_to_DATA_invalid

OE_EXT

WD_TRIG

DATA_to_WD_TRIG

output_event_delay

Figure 38: Digital Output timing

OUTVALID

OUT_ENA_valid

OUT_ENA_invalid

OUTVALID

OUT_ENA

Figure 39: OUT_ENA timing

1 2 ... 87 88 89 90 91 92 93 94 95 96 97 ... 125 126

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Instrukcja Użytkownika Strona 92